This invention relates generally to power management techniques and more particularly to the application of the same to computer systems.
Power management in computer systems has become increasingly important with the advent of laptop and notebook computers. These portable computers operate on batteries, usually nickel-cadmium (nicad) or nickel-metal-hydride. Unfortunately, advances in battery technology have not kept pace with the increasing power demands of modern portable computers. The shift from black and white to color displays has added a tremendous additional demand on power as well as the increases in microprocessor clock rate and main memory size.
In order to extend the battery life, computer systems have employed so called "power management" techniques. These techniques attempt to minimize the power consumption of the system by reducing the power consumption of the individual subsystems of the overall computer system. An example of a prior art computer system 10 having power management is shown in FIG. 1. This system 10 includes a central processing unit (CPU) or microprocessor 12, a keyboard 16, a disk 18, a display 20, a main memory subsystem 22, and an I/O subsystem 24. The CPU 12 is coupled to the subsystems over a bus 14. There are two primary power management techniques. The first is controlling the clock rate of the subsystems and the second involves controlling the power provided to the same, i.e., turning off of idle components.
As is known in the art, power consumption of a CMOS integrated circuit (IC) is directly proportional to the switching frequency of the IC. The switching frequency is in turn controlled by the clock rate provided to the IC. Accordingly, by adjusting the clock rate, the power consumed by the IC can be reduced. The system 10 takes advantage of this by reducing or even stopping the clock signal provided to the various subsystems under certain conditions. Those conditions are typically that the subsystem has been idle for a predetermined amount of time. The activity is monitored by the microprocessor 12 by detecting either writes or reads at predetermined memory locations. If no such memory activity has occurred within a predetermined period of time, the microprocessor assumes that it can safely shut down the subsystem without adversely effecting the system.
The system 10 also includes five switches S1-S5 that are individually controllable by the microprocessor 12. These switches can either control the power supplied to the corresponding subsystems or, alternatively, the clock frequency supplied thereto. In the event the switch controls the clock frequency there is also a corresponding clock divider circuit (not shown) that divides down the clock signal, typically in multiples of two, or reduces the clock frequency to zero. The microprocessor 12, after detecting the predetermined idle period, sets the switch such as switch S3 by asserting a signal on a corresponding line coupled between the microprocessor and the switch such as line 26. This causes the switch to switch to the appropriate state, which thereby causes either the clock or power to be adjusted. When the subsystem becomes active the microprocessor 12 deasserts the signal thereby switching the state back to its normal position, which either sets the clock frequency to its normal operating frequency or reapplies power to the subsystem.
In either case the subsystem is typically not immediately available after the microprocessor activates or "wakes up" the subsystem. Accordingly, the microprocessor 12 must wait a predetermined amount of time before the subsystem is fully functional again. This is typically handled by an interrupt service routing which is invoked by a non-maskable interrupt. The interrupt service routine then insures that the subsystem is fully operational before passing control back to the system level application that attempted to access the subsystem. Such is the system implemented by Intel in its Intel 486SL, Advanced Micro Devices AM386DXLV, and Chipset Technologies Superstate system management architecture.
All of these techniques focus on reducing the power of the individual subsystems. Although the clock rate of the microprocessor can be reduced (such as shown in FIG. 1), this provides a very coarse level of control over the power dissipated by the microprocessor itself. Moreover, reducing the clock frequency produces a proportional decrease in the performance of the system. The microprocessor 12 goes to sleep except for some internal logic that monitors the bus activity.
Several other approaches have focused on power management at the microprocessor or "chip" level rather than at the system level. These chip-level approaches dynamically "sense" the instructions in the instruction stream and shut-down the whole chip or portions of the chip not required to execute those instructions. The PowerPC microprocessor, a joint development effort by IBM, Motorola and Apple Computer, uses such an approach. In the PowerPC there are four different power states: Full On, Doze, Nap, and Sleep. The PowerPC architecture includes a three power-saving mode bits that specify which of these four modes the chip is placed in. Software, typically the operating system, sets the mode by writing an appropriate value to the three power-saving mode bits. When set in the "Full On" power mode, the Dynamic Power management hardware of the PowerPC microprocessor disables those functional units not required to execute the instructions of the instruction stream that have been received by the microprocessor by removing or gating the clock from those functional units. In the "Doze" mode, all functional units are disabled by the same method, with the exception of the bus snooping logic and time base decrementer. The bus snooping logic is additionally disabled in the "Nap" mode. In the least consumptive "Sleep" mode, the system clock (SYSCLK) can be removed and the phase-locked-loop (PLL) disabled.
The Pentium microprocessor manufactured by Intel uses a similar approach to reduce power consumption of its internal floating point unit. The Pentium dynamically senses the current instructions and shuts down the clock for that unit when there is no floating point activity, i.e., no floating point instructions are being sent to the floating point unit.
U.S. Pat. No. 5,388,265 to Volk entitled "Method and Apparatus for Placing an Integrated Circuit Chip in a Reduced Power Consumption State" uses a similar approach except this approach dynamically turns off the entire chip when a certain lack of chip activity is detected. The turn off is performed by dedicated hardware that monitors the activity and reduces the power consumption of the entire chip. U.S. Pat. No. 5,276,889 to Shiraishi et al., entitled "Microprocessor having Built-in Synchronous Memory with Power-Saving Feature" reduces the power consumption of an on-chip synchronous memory by disabling the memory when the memory is not required by the currently executing instructions. An instruction decoder dynamically monitors the instruction stream and deasserts a memory enable signal to turn off the memory when instructions that do not use the memory are executed.
The problem with these "dynamic" approaches is that they impose a burden on the hardware to monitor and detect the instruction stream. This may compromise the clock cycle time in a heavily pipelined microprocessor. In addition, the hardware has difficulty looking ahead to determine whether certain instructions are going to be issued. The detection circuitry can check the queued instructions in the instruction buffer; however, this provides an advance warning of only a limited number of instructions. This advance warning may be insufficient to have the functional unit fully operational before the instruction is to be executed. Thus, the pipeline must be stalled in order to allow the unit to wake up.
Another approach is taught in U.S. Pat. No. 5,142,684 to Perry, et al. entitled "Power Conservation in Microprocessor Controlled Devices." That approach uses two processors--one high speed processor which runs foreground tasks at variable speeds and a low speed processor which executes background tasks. The low speed processor invokes the high speed processor only when computationally intensive foreground tasks are scheduled. This conserves power by using the low speed processor for most tasks and only using the high-speed, and therefore high power consumption, processor when required. A further level of power control is provided by software. Embedded in each subroutine is a clock control code that controls the clock rate of the high-speed processor clock. The high-speed processor reads this code and then writes the code out to an application specific integrated circuit (ASIC), which divides down the high-speed clock by a predetermined amount depending on the value of the code. Thus, an entire task is run at a given clock speed. The problem with this approach is that it requires a second processor, which adds cost and complexity to a design.
Accordingly, a need remains for a microprocessor with power management facilities, which does not suffer from the problems of the prior art.